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Cache write generate for parallel image processing on shared memory architectures

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3 Author(s)
C. M. Wittenbrink ; Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA ; A. K. Somani ; Chung-Ho Chen

We investigate cache write generate, our cache mode invention. We demonstrate that for parallel image processing applications, the new mode improves main memory bandwidth, CPU efficiency, cache hits, and cache latency. We use register level simulations validated by the UW-Proteus system. Many memory, cache, and processor configurations are evaluated

Published in:

IEEE Transactions on Image Processing  (Volume:5 ,  Issue: 7 )