By Topic

A hardware annealing method for optimal solutions on cellular neural networks

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
S. H. Bang ; Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA ; B. J. Sheu ; E. Y. Chou

An engineering annealing method, called hardware annealing, for optimal solutions on cellular neural networks is presented. Cellular neural networks have great potential in solving many important scientific problems in signal processing and optimization by use of pre-determined templates. Hardware annealing, which is a parallel version of effective mean-field annealing in analog networks, is a highly efficient method to find optimal solutions on cellular neural networks. It does not require any iterative stochastic procedure and henceforth can be very fast. The landscape of the network energy function is first adapted so that the whole annealing process does not get stuck at a local minimum at the beginning of searching for optimal solutions by adjusting each neuron to a low voltage gain. Then, the hardware annealing searches for the globally minimum energy state by continuously increasing the gain of neurons. The globally optimal equilibrium state is reached when each neuron is at its maximum voltage gain. The robustness of this proposed hardware annealing method for global optimization is assessed by analysis of the eigenvalues in a corresponding dynamical system model

Published in:

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing  (Volume:43 ,  Issue: 6 )