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In this paper we present a new approach to solving the false path problem. The method is based on our previous work on Timed Boolean Algebra . Given a logic circuit, we first derive timed Boolean expressions to model its dynamic behavior. Then, for each term in the expressions, we compute its corresponding sensitizability function, expressed in conjunction normal form; and use an expression in product form to approximate the function. Finally we remove the redundant terms whose sensitizability functions are not satisfiable and determine the maximal delays from the terms remained. Complexity analysis shows that our method identifies false paths and computes delays for sensitizable paths in polynomial time, while experimental results on ISCAS benchmark circuits prove its better efficiency and effectiveness.