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The authors propose a divider structure that combines a novel self timed ring structure and a carry-propagation-free division algorithm. The self-timed ring structure enables the divider to compute at a speed comparable to that of previously designed dividers with less silicon area. By exploiting the carry-propagation-free division algorithm, an even better performance can be achieved. The authors designed a layout of 54 b divider using 1.2 /spl mu/m CMOS technology and measured the area and speed. A speed of 135 ns per worst case division was obtained on 5.7 mm/sup 2/ of silicon area.