By Topic

Automatic synthesis of dynamically configured pipelines supporting variable data initiation intervals

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Hong-Shin Jun ; Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea ; Sun-Young Hwang

The authors propose a new approach for synthesizing the dynamically configured pipelines supporting variable data initiation intervals (DIIs). Compared to the previous research where the pipeline synthesis is confined to those with fixed DIIs, the proposed system allows powerful design space exploration by removing the constraints of fixed DIIs. The proposed algorithm tries to optimize the area of pipeline structures by fully utilizing hardware resources to which abstract operations in high-level design descriptions are assigned, while meeting the given timing constraints in the clock cycle time, number of stages, and data initiation sequence. Experimental results on benchmarks show that new design points, efficient in speed and in area, can be found by removing the restriction of fixed DIIs in the synthesis of pipeline structures.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:4 ,  Issue: 2 )