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We describe high-level library mapping (HLLM), a technique that permits reuse of complex RT-level databook components (specifically ALUs). HLLM can be used to couple existing databook libraries, module generators and custom-designed components with the output of architectural or behavioral synthesis. In this paper, we define the problem of high-level library mapping, present some algorithmic formulations for HLLM of ALUs, and demonstrate the versatility of our approach on a variety of libraries. We also compare HLLM against the traditional mapping approach using logic synthesis. Our experiments show that HLLM for ALUs outperforms logic synthesis in area, delay, and runtime, indicating that HLLM is a promising approach for reuse of datapath components in architectural design and high-level synthesis.