Electromigration reliability is a key concern for implementation of low dielectric constant (low κ) materials for on-chip interconnects. To address this problem, we have carried out a comparative study of electromigration performance for Al(0.5 wt% Cu) line structures formed with tetraethylorthosilicate (TEOS)-based SiO2 and a low κ polymeric dielectric, poly(arylene ether) (PAE). The test structures consisted of 800 μm long single-level line structures with adjacent extrusion monitor lines. Resistometric measurements were performed to measure electromigration lifetime. To supplement lifetime measurements, x-ray diffraction and transmission electron microscopy were used to measure overall grain size and grain orientation distributions, and electron backscattering diffraction was applied to determine local grain orientation and grain boundary characteristics. In addition, scanning electron microscopy was used to examine void morphology. Microstructural analysis has revealed a larger grain size and enhanced <111> texture in the PAE passivated Al lines compared to TEOS SiO2 passivated lines. The difference in microstructure is attributed to a high temperature process used to cure the PAE which is absent from the processing of the TEOS SiO2 samples. The improved electromigration performance can be attributed to the larger grain size and decreased grain misorientation in the PAE passivated lines. © 1998 American Institute of Physics.