The dielectric breakdown of gate oxide layers with thickness of 35 and 9.3 nm in metal-oxide-semiconductor capacitors with a n+ polycrystalline Si/SiO2/n- Si stack was investigated. Breakdown was characterized in a particular circuit configuration by following the time evolution of voltage, current, and power through the capacitor with a time resolution of the order of 2 ns. A detailed morphological characterization of the damaged samples by emission and transmission electron microscopy is shown and discussed. The results of the morphological analysis and of the electrical measurements are quantitatively discussed by simulating, through heat-flow calculations, the time evolution of the temperature in the regions interested to the breakdown phenomenon. © 1998 American Institute of Physics.