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Task-processor mapping for real-time parallel systems using genetic algorithms with hardware-in-the-loop

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3 Author(s)
Baxter, M.J. ; Sheffield Univ., UK ; Tokhi, M.O. ; Fleming, P.J.

This paper discusses the application of genetic algorithms (GAs) to the challenging problem of task to processor mapping in the field of real-time parallel processing. Mapping is the off-line allocation of the tasks that represent a parallelised algorithm across a multi-processor architecture. Here, the objective of the optimisation process is to tune the mapping in order to minimise the algorithm cycle time. This paper examines a GA approach for this, and applies it to the mapping of a number of demanding real-time control algorithms. Initially, a simple parallel architecture model is used as the objective function. This leads to the embedding of the target hardware within the objective function, to improve the performance of the GA. The effectiveness of these GA approaches are compared to the results of simple heuristic. Further enhancements in the GA, such as integrating financial cost in the optimisation process and the determination of an optimal parallel architecture, are finally discussed

Published in:

Genetic Algorithms in Engineering Systems: Innovations and Applications, 1995. GALESIA. First International Conference on (Conf. Publ. No. 414)

Date of Conference:

12-14 Sep 1995