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A combined packet classifier and scheduler towards Net-Centric Multimedia Processor design

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4 Author(s)
Mohanty, S.P. ; VLSI Design & CAD Lab. (VDCL), Univ. of North Texas, Denton, TX ; Ghai, D. ; Kougianos, E. ; Patra, P.

We introduce a net-centric multimedia processor (NMP) with built-in digital rights management (DRM) facilities to facilitate Internet protocol packet processing and video processing without use of the main CPU. Packet classification and scheduling are the two most computational intensive operations. In this paper we propose an algorithm and architecture which can perform simultaneous classification and scheduling towards high-performance and power-efficient realization of the NMP. The architecture is prototyped in VHDL and simulated for power, frequency, logic usage and throughput for 4 different logic families in the Xilinx environment.

Published in:

Consumer Electronics, 2009. ICCE '09. Digest of Technical Papers International Conference on

Date of Conference:

10-14 Jan. 2009