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Low-voltage low-power double bulk mixer for direct conversion receiver in 65nm CMOS

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3 Author(s)
Schweiger, K. ; Inst. of Electr. Meas. & Circuit Design, Vienna Univ. of Technol., Vienna ; Uhrmann, H. ; Zimmermann, H.

An innovative design with simulation results of a low-voltage bulk driven mixer for direct conversion receiver is presented. The circuit is designed in a 65 nm digital CMOS process without analog extensions. It offers a conversion gain of 22 dB at a clock frequency of 1.5 GHz for GALILEO/GPS applications. The design is capable of operating at up to 7 GHz with only 3 dB gain decrease. The simulated noise figure is 27 dB with a power consumption of 730 muW. Simulations at a supply voltage of 0.9 V instead of 1.2 V show a gain decrease of only 3 dB while the noise figure increases by 2 dB.

Published in:

Design and Diagnostics of Electronic Circuits & Systems, 2009. DDECS '09. 12th International Symposium on

Date of Conference:

15-17 April 2009