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The paper deals with the problems of input variables assigning to the free and bounded sets during logic function decomposition. The Ashenhurst decomposition is considered with respect to implementation of logic functions in LUT based FPGA. The method of finding profitable input variables partitioning is based on utilisation of Logic Differential Calculus. The elaborated method is very convenient especially if decomposition is carried out in Reed-Muller spectral domain because the Boolean differentials are easy calculated from Reed-Muller form of logic function which is simply calculated as reverse Reed-Muller transform. The obtained results are very promising.