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Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS

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1 Author(s)
Gielen, G. ; Dept. Elektrotechniek, Katholieke Univ. Leuven, Leuven

With the advanced scaling of CMOS technology in the nanometer range, highly integrated mixed-signal systems can be designed. The use of nanometer CMOS, however, poses many challenges. This keynote presentation gives an overview of problems due to increased variability and reliability. Both have to be addressed by the designer, either at IC design time or through reconfiguration at IC run time. Design tools for the efficient analysis and identification of reliability problems in analog circuits is described. Also, run-time circuit adaptation techniques are presented that allow a circuit to recover from degradation failures.

Published in:

Design and Diagnostics of Electronic Circuits & Systems, 2009. DDECS '09. 12th International Symposium on

Date of Conference:

15-17 April 2009