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Reducing Power Consumption with Relaxed Quasi Delay-Insensitive Circuits

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2 Author(s)
Christopher LaFrieda ; Comput. Syst. Lab., Cornell Univ., Ithaca, NY ; Rajit Manohar

This paper introduces novel circuits to mitigate power consumption in asynchronous logic. By exposing a preexisting timing assumption in quasi-delay insensitive (QDI) circuits, we develop a set of circuit templates that reduce dynamic power consumption while maintaining the robustness of QDI circuits. We refer to these as relaxed quasi delay-insensitive circuits (RQDI). Power consumption is reduced in four ways. First, we present a circuit template that saves power by reducing the logic required to generate enable/acknowledge signals. Second, we develop voltage converters for asynchronous channels that allow non-performance critical components to be moved to lower voltage domains. Third, we propose a circuit template that improves upon the use of multiple voltage domains by keeping the data logic in the high voltage domain, but moves the enable/acknowledge logic to the low voltage domain. Fourth, we utilize a novel 2-phase buffer to half the switching in global routing and static switching networks. Experiments show that we can reduce energy by 30-50%, with a minimal impact on area and performance.

Published in:

Asynchronous Circuits and Systems, 2009. ASYNC '09. 15th IEEE Symposium on

Date of Conference:

17-20 May 2009