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GHz Asynchronous SRAM in 65nm

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2 Author(s)
Dama, J. ; Fulcrum Microsyst., Calabasas, CA ; Lines, A.

This paper details the design of > 1 GHz pipelined asynchronous SRAMs in TSMC's 65 nm GP process. We show how targeted timing assumptions improve an otherwise quasi delay-insensitive (QDI) design. The speed, area, and power of our SRAMs are compared to commercially available synchronous SRAMs in the same technology. We also present novel techniques for implementing large pseudo dual-ported memories that support simultaneous reads and writes. The most sophisticated of three designs yields a fully provisioned dual-ported memory using multiple single-ported banks connected by dual-ported buses, plus a small side-band memory to avoid bank conflicts. We discuss our solutions for manufacturing defects, soft-errors, and analog robustness with attention to .advantages and challenges of our asynchronous methodology. Laboratory measurements of a test-chip demonstrate correct functionality at speeds well over a GHz. Our single-ported SRAM designs are larger but faster than the alternate synchronous designs, while our novel dual-ported implementations can be both smaller and much faster. These technology advantages lead directly to competitive advantages for our future commercial products.

Published in:

Asynchronous Circuits and Systems, 2009. ASYNC '09. 15th IEEE Symposium on

Date of Conference:

17-20 May 2009