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Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip Links

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2 Author(s)
Bainbridge, W.J. ; Silistix, Manchester ; Salisbury, S.J.

To the casual observer, glitches occurring in quasi delay-insensitive logic would appear to cause incorrect operation and render the circuits unusable. This paper presents an informal analysis of the effects of glitches occurring on the long interconnect wires connecting logical units of a network-on-chip (NoC) using quasi delay-insensitive (QDI) techniques. This is followed by the introduction and analysis of a set of techniques to reduce the likelihood and impact of such hazards affecting the circuit. Post layout area and performance impacts are presented for a 90 nm process.

Published in:

Asynchronous Circuits and Systems, 2009. ASYNC '09. 15th IEEE Symposium on

Date of Conference:

17-20 May 2009