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A model for parallel simulation of distributed shared memory

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3 Author(s)
Barriga, Luis ; Dept. of Teleinf., R. Inst. of Technol., Stockholm, Sweden ; Brorsson, M. ; Rassul Ayani

We present an execution model for parallel simulation of a distributed shared memory architecture. The model captures the processor-memory interaction and abstracts the memory subsystem. Using this model we show how parallel, on-line, partially-ordered memory traces can be correctly predicted without interacting with the memory subsystem. We also outline a parallel optimistic memory simulator that uses these traces, finds a global order among all events, and returns correct data and timing to each processor. A first evaluation of the amount of concurrency that our model can extract for an ideal multiprocessor shows that processors may execute relatively long instruction sequences without violating the causality constraints. However parallel simulation efficiency is highly dependent on the memory consistency model and the application characteristics

Published in:

Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 1996. MASCOTS '96., Proceedings of the Fourth International Workshop on

Date of Conference:

1-3 Feb 1996