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The design and simulation of the PACE prototype architecture

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3 Author(s)
F. Z. Ieromnimon ; Dept. of Comput. Sci., Essex Univ., Colchester, UK ; T. J. Reynolds ; M. E. Waite

We present a case study of the use of a Unix/C/Verilog production environment to aid the design, from concept to physical prototype, of the PACE parallel graph rewriting architecture. The entire architecture has been modelled, so that simulated runs of complete programs are possible. The architecture's model is currently being refined towards a component by component detailed hardware design

Published in:

Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 1996. MASCOTS '96., Proceedings of the Fourth International Workshop on

Date of Conference:

1-3 Feb 1996