Cart (Loading....) | Create Account
Close category search window
 

The design and simulation of the PACE prototype architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Ieromnimon, F.Z. ; Dept. of Comput. Sci., Essex Univ., Colchester, UK ; Reynolds, T.J. ; Waite, M.E.

We present a case study of the use of a Unix/C/Verilog production environment to aid the design, from concept to physical prototype, of the PACE parallel graph rewriting architecture. The entire architecture has been modelled, so that simulated runs of complete programs are possible. The architecture's model is currently being refined towards a component by component detailed hardware design

Published in:

Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 1996. MASCOTS '96., Proceedings of the Fourth International Workshop on

Date of Conference:

1-3 Feb 1996

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.