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Transaction processing workloads-a comparison to the SPEC benchmarks using memory hierarchy performance studies

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3 Author(s)
Thompson, G.D. ; Intel Corp., Santa Clara, CA, USA ; Nelson, B.E. ; Flanangan, J.K.

The study analyzes the memory hierarchy performance of three SPEC benchmarks and two TPC benchmarks. It finds large differences between the benchmarks in instruction cache miss rates and smaller differences in data cache miss rates. It then breaks all of the miss rates down in their components: context switch misses, user misses, supervisor misses, and collision misses. It demonstrates that context switches contribute little to the miss rates as do collision misses. Finally, using temporal locality graphs, it shows that the inherent locality differences between the reference streams is the main cause of miss rate differences between the various benchmarks

Published in:

Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 1996. MASCOTS '96., Proceedings of the Fourth International Workshop on

Date of Conference:

1-3 Feb 1996