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Exact Performance Estimates for Multiprocessor Memory and Bus Interference

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2 Author(s)
Mark A. Holliday ; Department of Computer Science, University of Wisconsin, Madison, WI 53706.; Department of Computer Science, Duke University, Durham, NC 27706. ; Mary K. Vernon

Exact results are given for the processing power in a multibus multiprocessor with constant memory cycle times and geometric interrequest times. Both uniform and nonuniform memory accesses are considered. Such results have not previously been obtained. In order to derive these results we use a method of introducing time into Petri nets, called Generalized Timed Petri Nets (GTPN), that we have developed. We describe the GTPN and how it is applied to the multiprocessor interference question. We reach several new conclusions. A commonly used definition of processing power can lead to substantial underestimation of the true processing power of the system. If the real system has a constant memory access time and any number of buses, then assuming an exponential access time can lead to substantial errors when estimating processing power probability distributions. In multibus systems with only a few buses a critical memory interrequest time exists. Performance close to that with a crossbar is attainable when the interrequest time is larger than the critical value. Obtaining these results illustrates the advantages, for moderate size state spaces, of the GTPN over simulation with respect to both model design and running time.

Published in:

IEEE Transactions on Computers  (Volume:C-36 ,  Issue: 1 )