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Some Aspects of the Dynamic Behavior of Hierarchical Memories

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1 Author(s)
Peter M. Fenwick ; Department of Computer Science, University of Auckland, Auckland, New Zealand.

In a computer system with a cache memory, the cache is effectively empty following a job switch, leading to a low hit rate and consequently lowered performance until the cache becomes reasonably full. The analysis shows that a job must run for several milliseconds before the average performance approaches that expected from a steady-state analysis. Care may therefore be needed in designing memory systems which have very high page-fault rates from main memory, or which include many levels in the memory hierarchy.

Published in:

IEEE Transactions on Computers  (Volume:C-34 ,  Issue: 6 )