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An Architecture for Bitonic Sorting with Optimal VLSI Performnance

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2 Author(s)
Bilardi, Gianfranco ; Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL. ; Preparata, Franco P.

We propose a class of designs of a new interconnection network, the pleated cube-connected cycles (PCCC), which can impleement stable bitonic sorting of n records of size q in area A = O(q2n2/T2), where T, the computation time, is in the range [¿(q log2 n), O(q ¿n/(q+ log n))]. Thus, this network is an AT2,/R-optimal bitonic sorter in the synchronous VLSI model of computation under the word-local restriction.

Published in:

Computers, IEEE Transactions on  (Volume:C-33 ,  Issue: 7 )