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Derivation of Minimal Test Sets for Monotonic Logic Circuits

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1 Author(s)
Dandapani, R. ; Department of Computer Science, The University of Iowa, Iowa City, Iowa 52240.

It is shown that the number of maximal false vertices and minimal true vertices is the minimum number of tests required to detect all s-a-1 and s-a-0 faults in any irredundant two-level realization of a 2-monotonic function.

Published in:

Computers, IEEE Transactions on  (Volume:C-22 ,  Issue: 7 )