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Mathematical ``Lower Bounds'' and the Logic Circuit Designer

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2 Author(s)
Farber, A. S. ; IBM Watson Research Ctr., Yorktown Heights, N. Y.; Responsive Data Processing Corporation, Mt, Kisco, N. Y. ; Schlig, E. S.

The use of published theorems on least times to perform arithmetic operations as aids in optimizing logic circuit designs is discussed. An illustrative example is presented involving the optimum maximum fan-in of circuits in a binary adder.

Published in:

Computers, IEEE Transactions on  (Volume:C-19 ,  Issue: 1 )

Date of Publication:

Jan. 1970

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