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A Scheme for Synchronizing High-Speed Logic: Part I

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2 Author(s)
Loomis, H.H. ; Department of Electrical Engineering, University of California, Davis, Calif. 95616. ; McCoy, Michael R.

In this paper we concern ourselves with the problem of obtaining high sequence rate sequential machines; machines which are constructed from realistic devices to operate at an input sequence rate which is independent of the machine complexity. To accomplish this result we have only to show a construction to realize acceptably synchronous devices from badly timed, restricted fan-in and fan-out devices. Once a complete set of synchronous devices is obtained, the results of Arden [1] and Arthurs [2] apply, and we know that any finite state machine has a realization using these devices which accepts input sequence members at a rate that is characteristic of the set of devices, not of the machine. The technique we propose for achieving this result is to produce a lattice of interconnected clock pulse sources called clock pulse propagators (CPP). These devices generate clock pulses which are acceptably synchronized with respect to the outputs of neighboring CPP's but are not required to be in synchronization with some machine-wide standard as in current practice. Once it is established that such a network is possible, techniques already known can be applied in the utilization of the clock pulses to synchronize logic and signals. Part I of the paper concerns the analysis of CPP networks and Part II1 covers the synthesis of sequential machines using CPP networks as clocking sources.

Published in:

Computers, IEEE Transactions on  (Volume:C-19 ,  Issue: 1 )

Date of Publication:

Jan. 1970

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