Cart (Loading....) | Create Account
Close category search window
 

Propagation of I/O-variables in massively parallel processor arrays

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Fimmel, D. ; Dept. of Electr. Eng., Tech. Univ. Dresden, Germany ; Merker, R.

The underlying design method for massively parallel processor arrays allows one to exploit parallelism in a broader range, because the I/O variables are not considered during the design process of a full-size array. As a consequence of this approach, a reallocation of the I/O ports of the I/O variables at the boundary processors of the processor array is necessary. Algorithms are described for the reallocation of the I/O ports at the array boundaries, leading to a minimal additional latency and taking systolic constraints into account. Integer linear programming is used to solve the optimization problems that arise

Published in:

Parallel and Distributed Processing, 1996. PDP '96. Proceedings of the Fourth Euromicro Workshop on

Date of Conference:

24-26 Jan 1996

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.