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Characterization and Testing of Physical Failures in MOS Logic Circuits

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2 Author(s)
Banerjee, P. ; University of Illinois ; Abraham, J.A.

Studies indicate that the conventional stuck-at fault model is inadequate for modeling the effects of physical failures on MOS circuits. The authors illustrate various types of non-stuck-at behavior, such as indeterminate logic levels, timing errors, and alteration of logic functions. They discuss the generation of tests for detecting the failures in simple and complex MOS circuits. An advantage of testing for failures at the circuit level is that in some cases it may be possible to utilize the structural properties of the circuit to design a much simpler test set compared to one that is based on a gatelevel description of the circuit. The authors outline a methodology whereby functional fault models are derived by studying the effects of physical failures at the circuit level for functional modules.

Published in:

Design & Test of Computers, IEEE  (Volume:1 ,  Issue: 3 )