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Optimizing power in ASIC behavioral synthesis

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2 Author(s)
San Martin, R. ; Nortel Technol., Ottawa, Ont., Canada ; Knight, J.P.

Attacking power consumption at the behavioral level exploits an application's inherent parallelism to maintain performance while compensating for slower, less power-hungry operators. The authors' method and tool optimize and evaluate the effects of power-saving strategies on performance and silicon area

Published in:

Design & Test of Computers, IEEE  (Volume:13 ,  Issue: 2 )