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A loop routing approach for decreasing critical path delay

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2 Author(s)
Changge Qiao ; Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China ; Xianlong Hong

In this paper, we propose a loop routing performance optimization approach, which create loops in the existing routing trees for the purpose of decreasing delay of the selected critical path or maximum delay for a net. The interconnect tree is formulated as a tree of distributed transmission lines and Elmore delay is used for delay calculation. It is proven that the delay of a selected critical path or maximum delay for a net can be reduced dramatically by introducing a new link with appropriate R, C values between the reference node and the critical node in the existing tree topology. We give the wire length selection on the basis of pre-calculated time delay of node and the resistance and capacitance array. Experiments show the effectiveness of our approach for critical path delay minimization

Published in:

Solid-State and Integrated Circuit Technology, 1995 4th International Conference on

Date of Conference:

24-28 Oct 1995