By Topic

A low cost, fully integrated, event-driven, real-time control and data acquisition system for fusion experiments

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
4 Author(s)
Batista, A.J.N. ; Associação EURATOM/IST, Centro de Fusão Nuclear, Instituto Superior Técnico, Av. Rovisco Pais 1, 1049-001 Lisboa, Portugal ; Combo, A. ; Sousa, J. ; Varandas, C.A.F.

Your organization might have access to this article on the publisher's site. To check, click on this link:http://dx.doi.org/+10.1063/1.1534927 

A new, real-time, distributed, control and data acquisition system architecture for long duration fusion experiments was developed based on the new optical communications technologies and the “System on a Chip” methodology. The architecture integrates data routing, data storage, real-time data processing and control and data acquisition nodes, interconnected by a switched-packed, gigabit, point-to-point, communications network. The routing nodes provide connections to the autonomous storage and processing nodes through standard network links. The control and data acquisition nodes are connected to the routing nodes by specifically designed optical links which provide both data transport and timing/synchronism support. The acquired data are time stamped and can be dynamically processed for local control or sent to the external storage, the real-time processing or the control nodes. The standard processor and the reconfigurable field programmable gate array included in each node allow the programming of the data reduction, adaptive signal processing, and control algorithms from a high level system description language. All nodes will be controlled through an instrumentation-specific implementation of the Extensible Markup Language. A control and data acquisition node with 32 independent and galvanically isolated analog channels of 16 bits resolution is under development. All input signals are continuously and simultaneously sampled at a rate of 2 MSPS, time stamped, optionally digitally filtered, and stored in a large circular memory buffer. Three other node configuration sets will also be implemented: 16 channels, 20 MSPS, 16 bit; 8 channels, 100 MSPS, 12 bit; 2 channels, 1 GSPS, 8 bit. © 2003 American Institute of Physics.

Published in:

Review of Scientific Instruments  (Volume:74 ,  Issue: 3 )