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An efficient charge recovery logic circuit

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2 Author(s)
Yong Moon ; Inter-Univ. Semicond. Res. Centre, Seoul Nat. Univ., South Korea ; Deog-Kyoon Jeong

Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows four to six times power reduction with a practical loading and operation frequency range. An inductor-based supply clock generation circuit is proposed. Circuits are designed using 1.0-μm CMOS technology with a reduced threshold voltage of 0.2 V

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:31 ,  Issue: 4 )