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An 80-MOPS-peak high-speed and low-power-consumption 16-b digital signal processor

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11 Author(s)
Kabuo, H. ; Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka, Japan ; Okamoto, M. ; Tanaka, R. ; Yasoshima, H.
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This paper describes a 16-b fixed point digital signal processor (DSP), especially its multiply-accumulate (MAC) unit, memories, and instruction set. By adopting a redundant binary multiplier and a variable pipeline structure, this DSP's MAC unit, compared to a conventional MAC unit, consumes about 15% less power and operates 24% faster. Furthermore, its double-speed MAC mechanism can realize twice the performance of a single MAC operation while consuming only 69% more power. By being able to more finely control which portions of memory are activated, the data ROM and data RAM's precharge current was reduced to about 1/8 of the conventional ROM and RAMs. We redesigned the instruction set and reduced its width from 32 b to 24 b based on the analysis of data generated by simulating an application program on our previous DSP. The reduction in instruction width made our on-chip instruction memory size 33% smaller than the previous one. This chip is fabricated with a 0.5-μm double-metal-layer CMOS process and achieves 80-MOPS-peak double speed multiply-accumulate performance

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:31 ,  Issue: 4 )