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Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes

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4 Author(s)
A. Amerasekera ; Semicond. Process & Device Center, Texas Instrum. Inc., Dallas, TX, USA ; C. Duvvury ; V. Reddy ; M. Rodder

The effect of salicides and the influence of the local substrate potential on ESD performance of deep submicron nMOS transistors have been studied. It is shown that salicidation causes a strong dependence of ESD performance on effective channel length in these devices. Salicides also impact the behavior of the lateral npn parasitic bipolar transistor by affecting the emitter efficiency. A higher local substrate potential has been shown to have a positive impact on ESD performance. Based on these results we have designed and demonstrated a substrate triggered nMOS protection circuit which provides >2 kV ESD performance in a fully salicided process

Published in:

Electron Devices Meeting, 1995. IEDM '95., International

Date of Conference:

10-13 Dec 1995