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“NET-AN” a full three-dimensional parasitic interconnect distributed RLC extractor for large full chip applications

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9 Author(s)
Akcasu, O.E. ; OEA Int. Inc., Santa Clara, CA, USA ; Lu, J. ; Dalal, A. ; Mitra, S.
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A full 3D RLC extraction capability is presented which is suitable for very large nets on very large chips. The need, solution methodology, and usage in a real design environment are shown. The extracted parasitics and their effects on the delay/skew numbers are presented for real clock distribution circuits from real production designs, not test chips or special layouts

Published in:

Electron Devices Meeting, 1995. IEDM '95., International

Date of Conference:

10-13 Dec 1995