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A scaled 1.8 V, 0.18 μm gate length CMOS technology: device design and reliability considerations

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3 Author(s)
Rodder, M. ; Semicond. Process & Device Center, Texas Instrum. Inc., Dallas, TX, USA ; Aur, S. ; Chen, I.C.

Device design improvements for scaling to a high performance 1.8 V, 0.18 μm gate length CMOS technology are presented. nMOS with nominal Idrive(Idrivenom)=55 μA/μm drive (with toxacc=43 Å, toxinv=49 Å from C-V at Vgb=-4, +2.5V), Rsd<280 Ω-μm, Lgmin (minimum gate length at Ioff=1 nA/μm)=0.16 μm, and hot carrier lifetime ≫10 years is achieved. Increased As HDD dose, pocket implant, and RTA HDD anneal are required for simultaneous high Idrivenom, high carrier velocity vs. DIBL, and L gmin=0.16 μm. pMOS with Lgmin =0.16 μm and with Idrivenom=220 μα/μm is achieved. BF2 HDD plus RTA HDD anneal prior to sidewall deposition to eliminate interstitial enhanced B tail diffusion are utilized to form more abrupt pMOS HDD junctions. Super-steep retrograde (SSR) As channel profile reduces SCE and increases veff (and Idrive) vs. DIBL, but decreases veff (and Idrive) vs. Ioff, compared to a non-SSR profile. pMOS (Idrivenom)=220 μA/μm (with non-SSR profile) and nMOS Idrivenom)=550 μA/μm result in a 30% improvement in speed for the 1.8 V, 0.18 μm technology compared to a prior 2.5 V, 0.25 μm technology

Published in:

Electron Devices Meeting, 1995. IEDM '95., International

Date of Conference:

10-13 Dec 1995