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Initialization-Based Test Pattern Generation for Asynchronous Circuits

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1 Author(s)
Efthymiou, A. ; Sch. of Inf., Univ. of Edinburgh, Edinburgh, UK

A novel test pattern generation method for asynchronous circuits is described and evaluated in detail. The method combines conventional pattern generation with hazard-free state initialization. Any type of asynchronous circuit can be processed, and all stuck-at faults, even those inside state-holding elements, such as C-elements, are considered. The results on some of the largest benchmarks ever used for asynchronous circuit testing show fault coverage on the order of 99% with no area overhead for (quasi-)delay-insensitive datapath circuits.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:18 ,  Issue: 4 )