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Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus

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3 Author(s)
Junhee Yoo ; Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea ; Sungjoo Yoo ; Kiyoung Choi

On-chip bus design has a significant impact on the die area, power consumption, performance and design cycle of complex system-on-chips (SoCs). Especially, for high frequency systems having on-chip buses pipelined extensively to cope with long wire delay, a naive bus design may yield a significant area/power cost mostly due to bus pipeline cost. The topology, floorplan, and pipeline are the most important design factors that affect the cost and frequency of the on-chip bus. Since they are strongly correlated with each other, it is imperative to codesign all of the three. In this paper, we present an automated codesign method for cascaded crossbar bus design. We present CADBUS (CAscadeD crossbar BUS design tool), an automated tool for AXI-based cascaded crossbar bus architecture design. The primary objective of this study is to design a cascaded crossbar bus, including the topology/floorplan/bus pipelines, having minimum area/power cost while satisfying the given constraints of communication bandwidth/latency or frequency. Experimental results of the three industrial strength SoCs show that, compared to the existing approach, the proposed method gives as much as 11.6%-34.2% (9.9%-33.5%) savings in bus area (power consumption).

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:17 ,  Issue: 8 )