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We propose a floating-point serial divider for a single-flux quantum (SFQ) logic implementation based on a hardware algorithm of division using subtract and shift operations. Fast serial calculations are performed by utilizing the signed-digit representation. The divider is implemented with a regularly aligned pipeline structure called a systolic array. The processing element of the systolic array is designed using several logic gates unique to the SFQ circuits, to reduce the number of pipeline stages. As a result, high throughput and low latency is achieved with a small circuit size. The throughput approaches the maximum throughput of serial processing. A 4-bit divider was fabricated using the 2.5-kA/cm2 niobium process technology, and successful operation up to 19 GHz was demonstrated.