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This paper presents the first 150 GHz amplifier in a digital 65 nm CMOS technology. Design techniques to preserve raw transistor gain near fmax include layout optimization, dummy-prefilled microstrip lines (MSL) for design-rule compliance, and matching topologies which minimize passive element losses. To the authors' knowledge, the measured 8.3 dB gain, 6.3 dBm saturated output power (Psat), 1.5 dBm P1dB, 25.5 mW DC dissipation (PDC), and 27 GHz 3 dB BW are among the best in either CMOS or SiGe beyond 110GHz.
Date of Conference: 8-12 Feb. 2009