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The cost for screening test on wafer has continually increased each year; the test cost especially for low-price IC chips, for example, exceeds one-third of total chip cost. Furthermore, screening test on wafer to select good dies (Known- Good-Die) will become more significant to improve the yields of up-to-date packages such as Chip-on-Chip and 3D-LSI. Therefore, the cost reduction for screening test will be a key issue to maintain continuous LSI-performance scaling. This paper proposes a novel wireless DC voltage transmission technique which implements all the circuits for DC tests into the area of an inductor. There are two keys to this technique. The first one is a wireless DC voltage transceiver that can output DC voltage without any area- consuming circuits on the DUT-chip. The second one is a TX-rich digital calibration method that can correct the error of the DC voltage output without area-consuming calibration circuits on the DUT-chip.