A 0.1e- vertical FPN 4.7e- read noise 71dB DR CMOS image sensor with 13b column-parallel single-ended cyclic ADCs

The performance requirements of next-generation CMOS image sensors (CIS) have been increasing in terms of frame rate, read noise, dynamic range, as well as pixel resolution. In order to satisfy strict specifications, a column-parallel ADC is a key element in a state-of-the-art CIS. However, this architecture leads to side-effects such as vertical fixed pattern noise (VFPN) and read noise. In order to reduce these non-idealities, several techniques can be applied such as digital CDS using a single-slope ADC, and pre-amplified digital CDS using a SAR ADC. It is challenging to overcome the difficulty of compatibility between ADC speed and bit resolution, while maintaining low-noise performance and high dynamic range (DR). In this paper, a low-noise high-DR and high-speed CIS with a 13b column-parallel cyclic ADC based on a single-ended architecture is presented. The cyclic ADC requires 12 cycles for 13b resolution. The ADC requires identical conversions for reset and signals, within the limited horizontal time period, at a frame rate of over 300 fps, so as to achieve perfect digital CDS and ultra-low VFPN. In addition, lower total read noise is achieved without signal amplification by removing: (1) dual analog paths in fully differential circuits, (2) a common reference route, and (3) digital coupling noise. Published cyclic ADCs that are located in the column of a CIS have column pitch of 15 mum or larger. The circuits with the single-ended architecture presented in this paper are squeezed into 5.6 mum column pitch and can be applied to 2.8 mum-pitch pixels with double-side disposition.