By Topic

A 172mm2 32Gb MLC NAND flash memory in 34nm CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

34 Author(s)

As applications for NAND continue to grow and cost remains a primary market driver, it is necessary to deliver increased storage capacities at smaller process lithography while meeting high performance requirements. Design plays a pivotal role by providing architectures and design solutions that minimize the impact of bitline and wordline resistance and capacitance (RC) requirements and cell-reliability constraints. This paper presents a device that employs chip architecture, datapath, and analog architecture solutions that address these challenges while meeting high performance requirements. This 32 Gb MLC NAND delivers 50 mus tREAD, 900 mus tPR0G and 9 MB/s write throughput in a 34 nm technology.

Published in:

Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International

Date of Conference:

8-12 Feb. 2009