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A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS

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5 Author(s)
Yong Liu ; IBM T.J. Watson Res. Center, Yorktown Heights, NY ; Byungsub Kim ; Dickson, T.O. ; Bulzacchelli, J.F.
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The design of compact low-power I/O transceivers continues to be a challenge for both chip-to-chip and backplane applications. The introduction of dense fine-pitch silicon packaging technologies, that in principle are capable of supporting tens of thousands of high-data-rate I/O for local chip-to-chip interconnect, will make I/O area and power requirements even more stringent.This paper describes an alternative low-power compact I/O transceiver with RX equalization that achieves the required multi-bit postcursor cancellation without a high tap-count DFE. While this work targets data transmission over Si carrier links at rates up to 10Gb/s, it is also relevant to backplane channels.

Published in:

Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International

Date of Conference:

8-12 Feb. 2009