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A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile application

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18 Author(s)
Bong Hwa Jeong ; Hynix Semicond., Icheon, South Korea ; Jongwon Lee ; Yin Jae Lee ; Tae Jin Kang
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With the advent of high-performance multi-processing demands for real-time multimedia and broadband networking in battery-based mobile systems, high-speed and low power mobile SDRAM/DDRs are becoming increasingly important. We present an on-the-fly power-cut scheme that can be applied to mobile DRAM without any special modes and a global data-line repeater scheme to reduce the data-line delay. In addition, 4b data prefetch and a ZQ calibrated output driver scheme are used to achieve 4.3 GB/s/chip (1066 Mb/s/pin) bandwidth with 110 mW power dissipation.

Published in:

Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International

Date of Conference:

8-12 Feb. 2009

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