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The next-generation enterprise Xeonreg server processor consists of eight dual- threaded 64b Nehalem cores and a shared L3 cache. The system interface includes two on-chip memory controllers and supports multiple system topologies. This design has 2.3B transistors and is implemented in 45 nm CMOS using metal-gate high-K dielectric transistors and nine Cu interconnect layers. The thermal design power is 130 W.