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A 1/2.5-inch 8Mpixel CMOS image sensor with a staggered shared-pixel architecture and an FD-boost operation

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6 Author(s)
Tanaka, N. ; Toshiba Semicond., Yokohama ; Naruse, J. ; Mori, A. ; Okamoto, R.
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In this paper, a shared-pixel architecture in which the Gr pixel and the Gb pixel are designed to have the same layout structure, is introduced for suppression of the Gr/Gb sensitivity imbalance. In addition, a more effective FD-boost scheme that uses both gate-to-source capacitance (CGS) and gate-to-drain capacitance (CGD) is introduced to resolve the trade-off between dark random noise and FD capability, without adding any additional pixel-drive wiring.

Published in:

Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International

Date of Conference:

8-12 Feb. 2009