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Highly linear and low noise differential bipolar MOSFET down-converter in CMOS process

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3 Author(s)
Nam, I. ; Sch. of Electr. Eng., Pusan Nat. Univ., Busan ; Moon, H. ; Kwon, K.

A highly linear, low noise differential down-converter employing a new linearisation technique derived from composite transistors, i.e. nMOSFET and vertical NPN BJT, is proposed and implemented in a 0.18 mum CMOS technology. It draws 1 mA from a 2.5 V supply voltage and has a voltage gain of 13 dB, a double-sideband noise figure of 9.5 dB, an IIP2 of more than 49 dBm, and an IIP3 of 6.5 dBm.

Published in:

Electronics Letters  (Volume:45 ,  Issue: 11 )