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Admittance study of GaAs high-k metal-insulator-semiconductor capacitors with Si interface control layer

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2 Author(s)
Akazawa, Masamichi ; Research Center for Integrated Quantum Electronics (RCIQE) and Graduate School of Information Science and Technology, Hokkaido University, North-13 West-8, Sapporo 060-8628, Japan ; Hasegawa, Hideki

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Admittance behavior of high-k GaAs metal-insulator-semiconductor (MIS) capacitors having an ultrathin SiNx/Si interface control double layer has been investigated in detail. The measured admittance showed characteristic features that are difficult to explain by the standard Si metal-oxide-semiconductor theory. They include (1) vertical and horizontal types of frequency dispersion in C-V curves, (2) presence of offset conductance in G/ω-f plot, and (3) discrepancy between the surface potential from the high-frequency capacitance and the corresponding relaxation frequency of interface states. All of these features are tentatively explained in a unified manner by a new distributed pinning spot (DPS) model where the MIS interface consists of DPSs in addition to pinning-free regions. When the separation of pinning spots is small, the sample shows vertical type of frequency dispersion with almost bias-independent high-frequency capacitance corresponding to pinning near midgap. When pinning spots are widely separated, the C-V curves show horizontal type of frequency dispersion, each curve showing large capacitance variation with bias. This is due to flatband voltage shifts caused by effective interface state charge at the pinning spots. The pinning spot also gives rise to conductance offset. The discrepancy related to the relaxation frequency of interface states is explained by appearance of saddle points in the potential due to interaction between pinning spots and pinning-free region.

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Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures  (Volume:26 ,  Issue: 4 )