Highly efficient vertical outgassing channels for low-temperature InP-to-silicon direct wafer bonding on the silicon-on-insulator substrate

The authors report a highly efficient design for low-temperature, void-free InP-to-silicon direct wafer bonding on a silicon-on-insulator (SOI) substrate. By etching an array of small through holes in the top silicon layer, the generated gas by-products (H₂O, H₂) from bonding polymerization reactions and thus gaseous hydrocarbon can be absorbed and diffuse in the buried oxide layer, resulting in up to five orders of magnitude interfacial void density reduction (from ≫50 000 to ≤3 cm^-2). The required annealing time is reduced to less than 30 min, a ∼100X improvement compared to the previous outgassing design as well. Comprehensive studies in associated processing details, bonding surface energy, universality, and stability are also presented. Successful 50, 75, and 100 mm InP expitaxial layer transfer to the SOI substrate is also demonstrated, which indicates a total elimination of outgassing issues regardless of the wafer bonding dimension. Several incidental advantages leading to a flexible device design, low fabrication cost, and potential bonding strain relief are also discussed.