Cart (Loading....) | Create Account
Close category search window
 

Linewidth roughness transfer measured by critical dimension atomic force microscopy during plasma patterning of polysilicon gate transistors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Pargon, E. ; LTM-CNRS, 17 avenue des martyrs, 38054 Grenoble Cedex 9, France ; Martin, M. ; Thiault, J. ; Joubert, O.
more authors

Your organization might have access to this article on the publisher's site. To check, click on this link:http://dx.doi.org/+10.1116/1.2917071 

With the continuous scaling down of the critical dimensions (CDs) of semiconductor devices, the linewidth roughness (LWR) becomes a non-negligible parameter that needs to be controlled within 1 nm (at ) for the 32 nm node and beyond. In this article, the authors have used a CD-atomic force microscopy to investigate the evolution of the LWR during the subsequent lithography and plasma etching steps involved in the patterning of polysilicon transistor gates. The authors demonstrate that the LWR present on the etching mask [photoresist/bottom antireflective coating (BARC), SiO2 or amorphous carbon hard masks] right before the gate etching is transferred into the polysilicon during the HBr/Cl2/O2 gate etching step. Thus, the final polysilicon LWR directly is strongly dependent on the lithography and plasma etching steps preceding the gate etching step. The authors show that by applying plasma treatment to minimize the resist mask LWR prior to all the other etching steps or by optimizing the BARC opening plasma chemistry, the final polysilicon LWR can be minimized. The authors also demonstrate that the introduction of hard masks (SiO2 or amorphous carbon) helps to reduce further the final polysilicon gate LWR. Finally, the authors discuss the role of the ion bombardment in the smoothening/roughening of the pattern sidewalls during plasma processes.

Published in:

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures  (Volume:26 ,  Issue: 3 )

Date of Publication:

May 2008

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.